#include "shit_app.h"



/**************** 2015-6-9 16:01:38 The following code is for HR-HT error elusion ****************/
XTmrCtr TimerCounter; /* The instance of the Tmrctr Device */
XTmrCtr *TmrCtrInstancePtr;
/****************** 2015-6-9 16:01:38 The upper code is for HR-HT error elusion ******************/



/**************** 2015-6-9 16:01:38 The following code is for HR-HT error elusion ****************/
Xuint8 hr_exist[FRONT_BOARD_NUM];
Xuint8 hr_boot_ok[FRONT_BOARD_NUM];
Xuint8 hr_reboot[FRONT_BOARD_NUM];
Xuint8 hr_sys_reboot;
Xuint8 tmr_ok_times_g;
Xuint8 sys_boot_ok_g;
Xuint8 sys_rst_times_g;
Xuint8 sys_rst_overflow_g;


volatile int jj = 0x11223344;
/****************** 2015-6-9 16:01:38 The upper code is for HR-HT error elusion ******************/



/**************** 2015-6-9 16:01:38 The following code is for HR-HT error elusion ****************/
int init_rst_times_gpio(XGpio *Gpio_rst_times_ptr)
{
	xil_printf("*****init RST Times GPIO\n\r");


	XStatus Status;


	Status = XGpio_Initialize(Gpio_rst_times_ptr, XPAR_XPS_GPIO_2_DEVICE_ID);
	if (Status != XST_SUCCESS)
	{
		xil_printf("!!!Initialize XPAR_XPS_GPIO_2_DEVICE_ID failed\r\n");
		return XST_FAILURE;
	}

	XGpio_SetDataDirection(Gpio_rst_times_ptr, 1, 0xffffffff);  ///// 1 means input



	return XST_SUCCESS;
}


XStatus init_timer(Xuint16 DeviceId, Xuint8 TmrCtrNumber)
{
		xil_printf("*****init timer\n\r");


		XStatus Status;
		TmrCtrInstancePtr = &TimerCounter;

		/*
		* Initialize the timer counter so that it's ready to use,
		* specify the device ID that is generated in xparameters.h
		*/
		Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
		if (Status != XST_SUCCESS)
		{
		  return XST_FAILURE;
		}

		/*
		* Perform a self-test to ensure that the hardware was built
		* correctly, use the 1st timer in the device (0)
		*/
		Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);
		if (Status != XST_SUCCESS)
		{
		  return XST_FAILURE;
		}


		/*
		* Enable the Autoreload mode of the timer counters.
		*/
		XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber, XTC_AUTO_RELOAD_OPTION);



		/*
		* Set a reset value for the timer counter such that it will expire
		* eariler than letting it roll over from 0, the reset value is loaded
		* into the timer counter when it is started
		*/
		XTmrCtr_SetResetValue(TmrCtrInstancePtr, TmrCtrNumber, RESET_VALUE);


		return XST_SUCCESS;
}


void start_timer(Xuint16 DeviceId, Xuint8 TmrCtrNumber)
{
		/*
		* Start the timer counter such that it's incrementing by default
		*/
		XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber);
}



void init_sys_status(XGpio *Gpio_rst_times_ptr, XGpio *Gpio_245o_ptr)
{
	xil_printf("*****init sys status\r\n");

	u32 gpio_wr_data;
	u32 gpio_rd_data;



	if(jj == 0x11223344)
	{
#ifdef FK_HR_DBG
		xil_printf("\t\tjj: %08x\n\r", jj);
#endif
		gpio_wr_data = OTHER_BITS_VAL+(0<<HR_SYS_RST_BIT)+(0<<HR_BOOT_OK_BIT);
		XGpio_DiscreteWrite(Gpio_245o_ptr, 1, gpio_wr_data);

		jj = 0;
	}
	else
	{
		gpio_rd_data = XGpio_DiscreteRead(Gpio_rst_times_ptr, 1);
		sys_boot_ok_g = ((gpio_rd_data>>GPIO2_HR_BOOT_OK_BIT) & 0x00000001);
		sys_rst_times_g = ((gpio_rd_data>>2) & 0x0000007F);
		sys_rst_overflow_g = (sys_rst_times_g >= 3);

//		gpio_wr_data = OTHER_BITS_VAL+(0<<HR_SYS_RST_BIT)+(sys_boot_ok_g<<HR_BOOT_OK_BIT);
//		XGpio_DiscreteWrite(Gpio_245o_ptr, 1, gpio_wr_data);
//
#ifdef FK_HR_DBG
		xil_printf("\t\tjj: %08x\n\r", jj);
		xil_printf("\t\tsys_boot_ok_g: %02x\n\r", sys_boot_ok_g);
		xil_printf("\t\tsys_rst_times_g: %02x\n\r", sys_rst_times_g);
		xil_printf("\t\tsys_rst_overflow_g: %08x\n\r", sys_rst_overflow_g);
#endif
	}
}




void peek_sys_status(XGpio *Gpio_245o_ptr)
{
	xil_printf("\tpeek system status:\n\r");


	Xuint8 hr_idx;
	u32 gpio_wr_data;


	u32 Value;
	u32 wait_time;
	
	
	xil_printf("\t\tsys_boot_ok_g: %02x\n\r", sys_boot_ok_g);
	xil_printf("\t\ttmr_ok_times_g:%02x\n\r", tmr_ok_times_g);


	Value = XTmrCtr_GetValue(TmrCtrInstancePtr, TIMER_COUNTER_0);

	if(Value < HR_NO_ZHT_TIME)
	{
		return;
	}
	else if(tmr_ok_times_g<HR_ZHT_TIMES)
	{
		XTmrCtr_Reset(TmrCtrInstancePtr, TIMER_COUNTER_0);
		tmr_ok_times_g++;
		return;
	}
	else
	{
		hr_sys_reboot = 0;
		sys_boot_ok_g = 1;
		for(hr_idx=0; hr_idx<FRONT_BOARD_NUM; hr_idx++)
		{
			if(hr_exist[hr_idx] && (hr_boot_ok[hr_idx] != 0x0F))
			{
				hr_reboot[hr_idx] = 1;
	
				hr_sys_reboot = 1;
				sys_boot_ok_g = 0;
			}
		}
	}



#ifdef FK_HR_DBG
	xil_printf("\t\tsys_boot_ok_g:%d\n\r", sys_boot_ok_g);
	xil_printf("\t\thr_sys_reboot:%d\n\r", hr_sys_reboot);
#endif


	if(sys_boot_ok_g)
	{
		gpio_wr_data = OTHER_BITS_VAL+(0<<HR_SYS_RST_BIT)+(1<<HR_BOOT_OK_BIT);
		XGpio_DiscreteWrite(Gpio_245o_ptr, 1, gpio_wr_data);

		XTmrCtr_Stop(TmrCtrInstancePtr, TIMER_COUNTER_0);

		return;
	}
	else
	{
		xil_printf("-------------Not all HRs boot ok! System Will reboot!-------------\n\r");

		gpio_wr_data = OTHER_BITS_VAL+(0<<HR_SYS_RST_BIT)+(0<<HR_BOOT_OK_BIT);
		XGpio_DiscreteWrite(Gpio_245o_ptr, 1, gpio_wr_data);

#ifdef FK_HR_DBG
		xil_printf("\t\tgpio_wr_data:%08x\n\r", gpio_wr_data);
#endif

		for(wait_time=0; wait_time<1000; wait_time++);

		gpio_wr_data = OTHER_BITS_VAL+(1<<HR_SYS_RST_BIT)+(0<<HR_BOOT_OK_BIT);
		XGpio_DiscreteWrite(Gpio_245o_ptr, 1, gpio_wr_data);

#ifdef FK_HR_DBG
		xil_printf("\t\tgpio_wr_data:%08x\n\r", gpio_wr_data);
#endif

		for(wait_time=0; wait_time<1000; wait_time++);

		gpio_wr_data = OTHER_BITS_VAL+(0<<HR_SYS_RST_BIT)+(0<<HR_BOOT_OK_BIT);
		XGpio_DiscreteWrite(Gpio_245o_ptr, 1, gpio_wr_data);

#ifdef FK_HR_DBG
		xil_printf("\t\tgpio_wr_data:%08x\n\r", gpio_wr_data);
#endif

		sys_rst_times_g++;
		sys_rst_overflow_g = (sys_rst_times_g >= 3);

#ifdef FK_HR_DBG
		xil_printf("\t\tsys_rst_times_g:%02x\n\r", sys_rst_times_g);
		xil_printf("\t\tsys_rst_overflow_g:%02x\n\r", sys_rst_overflow_g);
#endif

		XTmrCtr_Reset(TmrCtrInstancePtr, TIMER_COUNTER_0);
		tmr_ok_times_g = 0;
	}
}






/****************** 2015-6-9 16:01:38 The upper code is for HR-HT error elusion ******************/




